A Methodology for the Efficient Circuit Extraction of Process Deformed Layouts

Process disturbances during the manufacture of an integrated circuit cause the fabricated circuit to vary from the design specifications. In some cases the variations are such that circuit faults result. The relationship between circuit faults and process disturbances is of interest because some applications such as yield prediction require information about what circuit faults are caused by a given set of process disturbances. Most of these applications perform a Monte Carlo simulation of process disturbances on a given layout, and then evaluate what circuit faults have resulted. This report details a methodology for performing the low level operations required to determine the process disturbance effects on layout structures. Some of the low level operations include circuit reextraction of layout geometries and the adjustment of layout dimensions. This report also describes a software implementation of our methodology called PRICE(Program for Region Circuit Extraction) and a MOS technology independent circuit extractor called ENTICE(ENhanced Technology Independent Circuit Extractor).